The present invention relates to a method of manufacturing a semiconductor device and, more specifically, to a method of manufacturing a stacked dynamic RAM (Random Access Memory).
Recently, with the increases in integration degrees of LSIs, dynamic RAMs (to be referred to as DRAMs hereinafter) have been micropatterned. However, if the area (capacitor area) of a portion which contributes to the capacitance of a memory cell capacitor is greatly decreased, the capacitance becomes too small to detect the accumulated electric charge. To increase the capacitor area per unit area, a memory cell having a cylinder-stacked structure has been proposed.
A conventional method of manufacturing a DRAM having a cylinder-stacked structure will be described below with reference to FIGS. 6A to 6D. As shown in FIG. 6A, a 0.4-.mu.m thick field oxide film 2 is formed on the surface of a p-type silicon substrate 1 by selective oxidation to partition active regions. A gate oxide film (not shown), a gate electrode (not shown), a source region 3, and a drain region (not shown) are formed in each active region to form a memory cell transistor with a known structure.
A 1-.mu.m thick BPSG (BoroPhosphoSilicate Glass) film 4 is formed on the silicon substrate 1 including the field oxide film 2, and a 0.2-.mu.m thick silicon oxide film 5 is formed on the BPSG film 4. Using lithography and etching, a contact hole 6 about 0.4 .mu.m square is formed in the BPSG film 4 and the silicon oxide film 5 to reach the source region 3. A 0.2-.mu.m thick polysilicon film 7 is formed on the silicon oxide film 5, and the interior of the contact hole 6 is filled with a polysilicon film 7a. A 0.4-.mu.m thick BPSG film 8 is formed on the polysilicon film 7a.
Using lithography and etching, the polysilicon film 7a and the BPSG film 8 are patterned to leave the polysilicon film 7a and the BPSG film 8 above the contact hole 6 including a peripheral portion. A 0.2-.mu.m thick polysilicon film 10a is formed on the silicon oxide film 5 and the BPSG film 8. FIG. 6A shows a state wherein the polysilicon film 10a is formed.
As shown in FIGS. 6B and 6C, the polysilicon film 10a on the upper surface of the BPSG film 8 is removed by anisotropic etching to leave the polysilicon film 10a only on the side surfaces of the polysilicon film 7a and the BPSG film 8, forming a side wall 10'. As shown in FIG. 6D, after the BPSG film 8 is removed, the polysilicon film 7a and the side wall 10' are rendered conductive by diffusing phosphorus therein, thereby forming the lower electrode of a capacitor.
A silicon nitride film is formed on the polysilicon film 7a and the side surface of the side wall 10' to form a capacitor insulating film (not shown). An upper electrode (not shown) serving as the counterelectrode of the capacitor is formed of polysilicon on the capacitor insulating film.
If the residue of the polysilicon film 10a remains on the silicon oxide film 5 upon anisotropically etching the polysilicon film 10a in order to form the side walls 10' in FIG. 6B, the capacitors of adjacent cells are short-circuited. For this reason, the etching time must be set long enough not to leave the residue of the polysilicon film 10a. The etching time is normally set about 50% longer than the time required to completely remove an etching target. Note that the ratio of the increase in etching time will be referred to as an over-etching ratio hereinafter.
If the polysilicon film 10a on the upper surface of the BPSG film 8 is removed, the etching rate of the polysilicon film 10a is increased by the microloading effect due to a decrease in occupying area ratio of the polysilicon film 10a with respect to the silicon substrate 1. For example, the etching rate, which is initially about 0.005 .mu.m/sec, increases to about 0.015 .mu.m/sec upon removing the polysilicon film 10a on the upper surface of the BPSG film 8. If an over-etching ratio of 50% is applied to the 0.2-.mu.m thick polysilicon film 10a in this situation, the height of the side wall 10' becomes smaller than that of the BPSG film 8 by about 0.3 .mu.m, as shown in FIG. 6C. If the side wall 10' becomes lower, the capacitor area decreases, resulting in a small cell capacity.
In the use of the cylinder-stacked capacitor, the cell size increases, compared to a case using a normal stacked capacitor. As shown in FIG. 6D, assuming the capacitor interval between adjacent cells is represented by s; the thickness of the side wall, w; the length from the end of the polysilicon film 7a to the connection hole 6, x; and the inner diameter of the connection hole 6, y, a short side length L1 of the cell having the cylinder-stacked capacitor is expressed by EQU L1=s+2w+2x+y
To the contrary, a short side length L2 of the cell having the normal stacked capacitor is shorter due to the absence of the side wall 10', and expressed by EQU L2=s+2x+y
In this case, the capacitor interval s and the inner diameter y of the connection hole 6 are determined by the resolution limitation of lithography, and the length x is determined by the alignment precision of lithography.
For example, according to the 0.4-.mu.m design rule of a DRAM memory cell, since the capacitor interval s and the inner diameter y of the connection hole 6 are 0.4 .mu.m, and the length x is 0.2 .mu.m for a normal stacked cell, the short side length of the cell is 1.2 .mu.m.
For a cylinder-stacked cell, the capacitor interval s can be set smaller than the resolution limitation value of lithography by the side wall thickness w. However, the adjacent cells must be sufficiently distant from each other so as to prevent short-circuiting therebetween, so that the lower limit of the capacitor interval s is about 0.25 .mu.m. If the side wall thickness w is set too small, the side wall 10' falls down due to a low mechanical strength. Therefore, the lower limit of the side wall thickness w is about 0.15 .mu.m. The length x and the inner diameter y of the connection hole 6 are respectively 0.2 .mu.m and 0.4 .mu.m as same as those of the normal stacked cell. Accordingly, the short side length of the cell is 1.35 .mu.m, longer than that of the normal stacked cell.
That is, although the capacitor interval s of the cylinder-stacked cell can be set shorter than that of the normal stacked cell, the increase amount 2w of the thickness of the side wall 10' is larger than the decrease amount of the capacitor interval s. As a result, the size of the cylinder-stacked cell becomes larger than that of the normal stacked cell.